Clock circuits are widely used in digital electronic devices and equipment for controlling logical operations and data flow. Moreover, adjustable phase clocks find wide applicability for timing adjustments and as active elements in clock recovery circuits and phase locked loops (PLLs). The PLL, in turn, is attractive for use in FM demodulators, stereo demodulators, tone detectors, frequency synthesizers, etc. Of course, a controllable phase clock can also be readily used to generate an adjustable frequency clock signal.
A conventional adjustable phase clock typically uses a voltage controlled oscillator (VCO) or a tapped delay line. Although the VCO permits a relatively large phase variability, such as desirable for a PLL, it suffers from frequency and phase instabilities inherent in an any inductor-capacitor (LC) or resistor-capacitor (RC) oscillator. A further drawback of the VCO based adjustable phase clock is that it requires a relatively large amount of analog circuitry to implement. The tapped delay line approach has a relatively high cost per delay.
Representative of a prior art clock synchronization circuit, U.S. Pat. No. 5,050,193 to Ponsard discloses a device including preprocessing circuitry for delivering to a PLL a preprocessed signal obtained from a replica of the incident digital signal staggered in time by a fraction of the cycle of the clock signal of the PLL. The device allows a fast synchronization of the clock of the PLL in relation to the incident signal, in particular at high transmission rates. The circuit includes delay means having four outputs providing, respectively four replicas of the incident digital signal, these replicas differing from each other by substantially a quarter cycle of the main clock. The delay means may be provided by an optical fiber, a conventional capacitor inductance delay circuit, or by a coaxial line.
U.S. Pat. No. 5,568,078 to Lee discloses a clock delay and compensation circuit for a PLL in a decoder of a video signal receiver. Phases of two input clocks are received by a phase comparative detector and compared to a divided reference clock from an oscillator of the phase comparative detector for obtaining a resultant phase error output. A duty ratio of the output clock is controlled in a duty controller to therefor the phase comparative detector to be used free from the duty ratio of the clock. A clock delay compensator performs correction of clock delay compensation for the system operated at high speed.
U.S. Pat. No. 5,278,457 to Fujita et al. discloses an electronic circuit including a portion for sensing temperature at a saturation state and for adjusting a clock signal phase to a fixed phase thereafter. The circuit includes two variable delay circuits controlled to have a same time delay. A phase adjustment control circuit receives a phase adjustment control signal from a service processor and has a function to switch between the phase adjusting mode and the phase fixing mode. The delays are fixed in the phase fixing mode to compensate for temperature.
Unfortunately, both conventional VCO and tapped delay line phase adjustable clocks suffer various drawbacks. The VCO phase adjustable clock suffers from frequency and phase instabilities inherent in its relatively complex analog circuitry, and the tapped delay line approach may be relatively expensive.